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题目内容：
用置数功能的4位循环移位寄存器电路，当load为1时，将4位数据d0，d1，d2，d3同步输入寄存器寄存，当load为0时，电路实现循环移位并输出q=q0q1q2q3，试将2选1MUX、D触发器分别定义为COMPONENT，并采用GENERATE语句例化两种器件，实现该电路。 EDA技术与VHDL设计 书本 P118 题目3.17 代码： 一，(Main-Top level Entity) ------------------This is Main Code,Please set it to Top level Entity------------------------ ----------------------------- --YZM-- (^@^)/ hi --2023.4.5 ----------------------------- library ieee; use ieee.std_logic_1164.all; entity Main is generic (Num:integer :=4);--4 is register_mux num; port( d_in: in std_logic_vector(0 to Num-1); q_out: out std_logic_vector(0 to Num-1); load,clk_now: in std_logic ); end Main; --########## register_mux########-- architecture register_mux of Main is component d_ff is port( d,clk: in std_logic; q: out std_logic ); end component; component mux_Two is port( mux_1,mux_2,mux_choose: in std_logic; mux_out: out std_logic ); end component; signal temp_mux:std_logic_vector(0 to Num-1); signal temp_register:std_logic_vector(0 to Num-1); begin e1:for i in 0 to (Num-1) generate --mux_1,mux_2,mux_choose, mux_out --d,clk,q --This is port of entity; ---------------------------------- temp1:if (i=0) generate line1: mux_Two port map( d_in(i),temp_register(Num-1),not load,temp_mux(i)); end generate temp1; temp2:if (i /=0) generate line2: mux_Two port map(d_in(i),temp_register(i-1),not load,temp_mux(i)); end generate temp2; line3: d_ff port map(temp_mux(i),clk_now,temp_register(i)); q_out(i) |
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