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ICC如何正确导出gds文件
时间:10-02
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各位好,问一个问题哈,我要把ICC布局布线后的gds设计导到virtuoso中进行修改,请问怎么设置ICC的set_write_stream_options?下面是我的report_write_stream_options的信息。icc_shell> report_write_stream_optionsReport stream out options***********************************Layer mapping file name: (null)Rename cell file name: (null)Child cell depth: 0Skip reference lib cells: falseText height width ratio: 1.000000Text width: 0.000000Flatten contact: falseFlatten contact array: falseContact prefix: $$Output notch: falseOutput gap: falseOutput fill: falseOutput outdated fill: falseOutput instance name as property: falseOutput geometry property: falseStrip backslash from instance net names: falseLong name length: -1Keep data type: falseBy layer number: Output compressed OASIS: falseOutput compressed GDSII: falseOutput pin as text: falseOutput pin as geometry: falsePin name magnitude: 1.000000Net name magnitude: 1.000000Rotate pin text by access direction: falseOutput net as text: falseOutput net as property: falseOutput net as plex: falseOutput odd pin: falseDesign intent struct name: (null)Critical name list: (null)Design intent layer mapping: (null)With original data: trueOutput design intent data: false***********************************谢谢~
do not know 学习中,求解释~ 同困惑 沒給 layer mapping file, ICC layer number 不一定與 Layout tf 的 layer number 對應.若 foundry 沒附. 自己寫. icc 写出来的gds layer 不全 建议写个hier的gds 然后再merge layer, layer number, layer mapping 上一篇:如何根据门电路结构算触发器setup,hold,propagation time 下一篇:encounter中进行IR drop 分析导出 如何正确 ICC 相关文章: icc 中对.5工艺DFM及导出GDS的选项设置 Cadence中怎样从Schematic电路/Layout版图导出Verilog网表? 请问DC综合后可以导出hspice网表吗? ICC导出GDS没有std cell? 从encounter里导出的gds在cadence里显示一堆VDD,VSS的label lefout.list怎么样从virtuoso主窗口导出? |
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